Wafer Scale Bonded Active Photonics Interposer

Background:

The field of integrated photonics has become increasingly important as demand for faster data transmission and higher bandwidth in computing and communications continues to rise. Photonic devices, which manipulate light to transmit information, offer significant advantages over traditional electronic components, including reduced energy consumption and the potential for much higher data rates. As data centers, high-performance computing, and telecommunications networks strive to meet the requirements of modern applications such as artificial intelligence and cloud computing, there is a pressing need for scalable, efficient, and cost-effective solutions that can integrate photonic and electronic components on a single platform. Current approaches to integrating photonic devices with electronic circuits often face significant challenges. Traditional methods typically rely on complex and costly processes such as flip-chip bonding or hybrid integration, which can be limited in scalability and yield. These methods may also introduce alignment issues, increased parasitic losses, and thermal management problems, ultimately restricting device performance and manufacturing throughput. Additionally, the lack of a standardized wafer-scale integration process for photonics and electronics hampers the ability to produce large volumes of high-quality, reliable devices, thereby limiting the widespread adoption of photonic technologies in commercial applications.

Technology Overview:

This technology is a wafer-scale bonded active photonics interposer, which enables the integration of photonic devices with electronic circuits at the wafer level. The process involves constructing an interposer base structure on a first wafer, which includes fabricating through vias that penetrate the substrate and forming metallization layers within a dielectric stack. Simultaneously, a photonics structure is built on a second wafer, where photonic devices are fabricated within its own dielectric stack. These two wafers are then bonded together, resulting in an interposer that combines the interposer base structure with the embedded photonic devices. This approach allows for high-density integration and precise alignment of photonic and electronic components, facilitating efficient optical and electrical interconnections. What differentiates this technology is its ability to achieve true wafer-scale integration of photonic and electronic functionalities, overcoming the limitations of traditional chip-level or package-level integration. By leveraging through-silicon vias and advanced wafer bonding techniques, the solution ensures low-loss, high-bandwidth communication between photonic devices and electronic circuits, while maintaining scalability for mass production. This method also enables the use of optimized materials and processes for both photonic and electronic components, enhancing performance and flexibility. As a result, the technology supports the development of next-generation high-speed data communication systems, optical interconnects, and advanced computing architectures with improved efficiency, miniaturization, and manufacturability.

Advantages:

•    Enables integration of photonics devices with electronic interposers at wafer scale
•    Facilitates fabrication of through vias for efficient electrical interconnection
•    Supports multilayer metallization within the interposer base for enhanced connectivity
•    Allows bonding of photonics structures to interposer base for compact, high-performance modules
•    Improves scalability and manufacturability of photonics-electronics hybrid systems
•    Enhances device performance by combining photonics and electronics in a single package

Applications:

•    High-speed optical data interconnects
•    Integrated photonic chip manufacturing
•    Data center optical networking
•    Telecommunications photonic modules
•    Advanced optical sensing platforms

Intellectual Property Summary:

3 US (Granted), TW (Granted), SG (Granted), KR (Granted), EP (Pending)

Stage of Development:

TRL 7

Licensing Status:

This technology is available for licensing.