Technology - Delta-Sigma Modulator Enabled Variable-Input Resolution In-Memory Computing SRAM Macro

Delta-Sigma Modulator Enabled Variable-Input Resolution In-Memory Computing SRAM Macro

An SRAM based IMC with higher linearity than the state of the art using delta-sigma modulators.


SRAM based IMC has gained significant attention due to its high energy efficiency and easy integration with CMOS ICs.  A fundamental limitation of SRAM based IMC is nonlinearity in the multiply-and-accumulate (MAC) operation.  For large values of MAC result, the proportional large discharge current through SRAM bitline pushes the access transistors into linear region and makes the discharge current, and hence the MAC result, a nonlinear function of bitline voltage. Recent works have tried to address this fundamental limitation by applying pulsed input activations and adding capacitors to SRAM bitcell for charge-domain computation which has much lower sensitivity to bitline voltage, and hence, higher linearity than current-domain computation in traditional SRAM bitcell. While pulsed input makes each SRAM bitcell linear, accumulation of partial products is still performed in current-domain and the overall MAC result is still nonlinear.  The capacitive SRAM in improves linearity over current-domain accumulation by making the MAC result independent of the discharge current.  However, linearity of MAC is still limited since the analog input is sampled on the capacitor in the bitcell through an NMOS switch.  The analog input activation modulates threshold voltage (Vth) of the NMOS switch making the voltage sampled on the capacitor nonlinear.  Vth drop in the NMOS capacitor also limits the maximum input swing that can be handled by the SRAM bitcell and restricts the supply voltage to relatively high values.

Technology Overview:

This work addresses the fundamental non-linearity in SRAM bitcell through two key techniques:
  1. using delta-sigma modulators (DSM) to convert analog input activations into a binary pulse train;
  2. using a 9T1C SRAM bitcell to perform computations in charge-domain.


Compared to SAR or flash ADC, resolution of DSM can be reconfigured easily without requiring changes in hardware.  For the same oversampling ratio (OSR), quantization noise-shaping in DSM allows higher resolution of input activation compared to the counter-based technique in which averages quantization error.  Use of CMOS switch instead of NMOS switch for sampling on the capacitor removes Vth drop in the sampled voltage and allows the SRAM bitcell to operate from very low supply voltages that improves power efficiency.


  • Artificial Intelligence
  • Modeling weather systems
  • Running data-intensive simulations

Intellectual Property Summary:

Provisional Patent Application 63/496,727 filed April 18, 2023.

Stage of Development:


Licensing Status:

Available for licensing or collaboration.

Patent Information: