Technology - Energy Efficient Steep Slope Cold Electron DIRAC Transistor

Energy Efficient Steep Slope Cold Electron DIRAC Transistor

Graphene-enabled Dirac-source "cold" electron transistor breaks the sub-60 mV/decade threshold and achieves current density over 1µA/µm


Power dissipation and energy efficiency in electronics are huge barriers facing the explosive growth of artificial intelligence (AI) and high-performance computing (HPC). Metal-oxide-semiconductor field-effect transistors (MOSFETs), driven by thermionic emission, require at least 60mV of gate voltage to increase the current by one order of magnitude at room temperature.  Steep-slope transistors are capable of switching faster than the limit of 60 mV/decade, owing to their sub-60-mV/decade subthreshold swing (SS) and lower gate voltage at the same performance over conventional MOSFETs.  By integrating emerging two-dimensional (2D) van der Waals materials with the unique nature of quantum confinement, this novel device invention has the transformative potential to practically realize low-power "beyond-CMOS" platforms.  The quantum-enabled transistor is based on 2D graphene (Gr) and transition metal dichalcogenides (TMDs) and represents a game changing technology for extending Moore's Law well into the next decade.

Technology Overview:

This technology demonstrates a Gr-enabled Dirac-source "cold" electron injection that possesses a more localized electron density distribution and a shorter thermal tail, compared to the conventional normal-source hot electron injection in 3D or 2D semiconductors.  The cold electron injection has been implemented in a monolayer MoS2 FET to introduce an "electronic refrigeration effect", which can lower the transport factor and thus enable an outstanding steep-slope switching (across three decades with a minimum SS of 29 mV/decade at room temperature), an excellent on/off ratio (~107), a strong on-current saturation (~10µA/µm), and especially a record-high sub-60-mV/decade current density (over 1µ/µm) compared to any tunnel FETs (TFETs) or negative capacitance FETs (NCFETs) using 2D or 3D channel materials.  The effective electron temperature was extracted to be ~145 K, on the basis of the energy distribution of the cold electrons at room temperature.  The device work level presents the 2D Dirac-source cold electron FET as a steep-slope transistor concept with the sub-60-mV/decade switching capability, which can benefit future energy-efficient nanoelectronics based on 2D materials.


This University at Buffalo technology is a successful demonstration of the world's first 2D Gr-enabled Dirac-source electron injection (DSEI) FET where monolayer Gr and MoS2 serve as the Dirac source and channel, respectively.  The prototypical device shows outstanding energy-efficient performance, including a sub-60-mV/decade switching (across for 3 decades at room temperature with the minimum SS of 29 mV/decade) and an excellent on/off ratio (~107).  Significantly, it demonstrates a record-high sub-60-mV/decade current density (over 1 µA/µm) compared to any state-of-the-art 2D or three-dimensional (3D) steep-slope FET technologies including TFETs or NCFETs.  This new transistor technology benefits low-power nanoelectronics and demonstrates the transformative potential of the steep-slope DSEI-FETs and DSEI-FinFETs for energy-efficient high-performance applications such as Artificial Intelligence (AI) and High Performance Computing (HPC) facilities.


  • Low power electronics
  • Artificial intelligence computing
  • High performance computing facilities

Intellectual Property Summary:

US Patent Application 17/358,500 filed June 25, 2021 US202110408272A1

Licensing Status:

Available for license or joint collaboration.

Patent Information: