Site-Specific Synthesis of 2D TMDs for High-Performance Nanoelectronic Devices

Background:

Two-dimensional transition metal dichalcogenides (TMDs) such as MoS₂ are promising channel materials for next-generation nanoelectronics, optoelectronics, and sensing platforms. Conventional synthesis methods rely on CVD growth on foreign substrates such as sapphire or gold, followed by mechanical transfer onto SiO₂/Si. These transfer steps introduce cracks, wrinkles, contamination, and interfacial traps that degrade device performance and limit CMOS compatibility. Existing selective-area growth methods often require complex substrate templating, metal seed layers, or post-growth lithography and etching, which increase process complexity and reduce material quality. A scalable, transfer-free, CMOS-compatible approach to site-specific 2D material growth remains a critical need.

Technology Overview:

This University at Buffalo technology introduces a lithographically defined, transfer-free CVD strategy for site-specific synthesis of MoS₂ directly on SiO₂/Si substrates. Patterned MoO₃ thin films serve as multifunctional precursors and dielectric layers. During sulfurization, MoO₃ is selectively converted into MoS₂ only in predefined regions, eliminating the need for post-growth patterning. Thermal annealing enables phase control of MoO₃, including formation of orthorhombic α-MoO₃ with a high dielectric constant (~35), allowing in-situ integration of a native high-k gate dielectric beneath the MoS₂ channel. By tuning sulfurization temperature, duration, and sulfur flux, the process yields either single-crystalline domains for high-performance logic devices or isotropic polycrystalline films for large-area applications. The resulting MoS₂/MoO₃/SiO₂ stack exhibits reduced interfacial trap densities, improved carrier transport, and enhanced metal-semiconductor contact properties.

Advantages:

• Transfer-free, wafer-scale growth directly on CMOS-compatible SiO₂/Si substrates
• Precise spatial control via lithographic precursor patterning without post-growth etching
• Multifunctional MoO₃ layer serving as both growth precursor and high-k dielectric (~35)
• Tunable crystallinity and grain structure through controlled sulfurization
• Reduced interfacial trap density and improved subthreshold swing
• Lower Schottky barrier height and contact resistance through interface engineering
• CMOS process compatibility and scalability for high-throughput manufacturing
• Demonstrated field-effect mobility ~20 cm²/V·s with enhanced ON-current and on/off ratios

Applications:

• Ultra-scaled, low-power field-effect transistors (FETs) for next-generation logic circuits
• Non-volatile memory, memristors, and neuromorphic computing elements
• RF and analog 2D transistor devices
• Integrated photodetectors, photosensors, LEDs, and photovoltaic layers
• Chemical and biosensors based on high-quality MoS₂ FET channels
• Pre-patterned 2D growth wafers and CVD process modules for semiconductor foundries
• Integration platforms for additional TMD materials including WS₂, MoSe₂, WSe₂, MoTe₂, and heterostructures

Intellectual Property Summary:

Patent protection is being pursued covering site-specific MoS₂ growth using patterned MoO₃ precursor layers, annealing-induced high-k dielectric integration, tunable crystallinity control, elimination of post-growth lithography, and enhanced contact engineering through MoO₃-assisted interface modulation.

Stage of Development:

Laboratory-scale synthesis demonstrated with fabricated MoS₂ FET devices showing improved electrical performance metrics.
TRL 4–5

Licensing Status:

Available for licensing and industry collaboration.