Tuning Characteristics of Films formed by Atomic Layer Deposition Through Underlayer Modification
The field of thin film deposition, particularly using atomic layer deposition (ALD), is critical for the fabrication of advanced electronic and quantum devices. Tantalum nitride (TaN) thin films are widely used as diffusion barriers, etch-stop layers, and in the formation of tunnel junctions for superconducting digital logic and quantum computing applications. As device architectures become increasingly complex and scaled, there is a growing demand for precise control over the electrical properties of these films, such as their resistivity and composition. This level of control is essential for optimizing device performance, enabling new functionalities, and ensuring compatibility with emerging technologies like superconducting quantum circuits and advanced CMOS interconnects. Current approaches to tailoring the properties of ALD TaN films face significant limitations. Conventional methods often rely on adjusting global process parameters, such as precursor chemistry or deposition temperature, which affect the entire wafer uniformly and lack the ability to locally tune film properties. Additionally, attempts to modify the underlayer to influence film growth typically result in thick or poorly controlled interfacial layers, which can degrade superconducting properties. These shortcomings hinder the formation of films with the required characteristics, limiting the performance of quantum devices and advanced semiconductor circuits. As a result, there is a pressing need for a method that enables spatially resolved, predictable, and ultra-thin modification of underlayers to achieve precise control over ALD TaN film characteristics without compromising device functionality.
This technology enables precise control over the electrical properties of tantalum nitride (TaN) thin films deposited by atomic layer deposition (ALD), achieved through targeted chemical modification of the substrate surface before film growth. The process pre-treats the surface in a variety of ways immediately prior to deposition, allowing for predictable tuning of the Ta:N ratio and resistivity of the resulting TaN film. This process supports the formation of TaN films with electrical characteristics ranging from highly conductive to highly resistive, and enables spatially selective tuning across a single wafer. The modified underlayer remains extremely thin, which is crucial for applications requiring Cooper pair transparency in superconducting devices, as well as for engineering tunnel junctions in quantum computing, superconducting digital logic circuits and for advanced CMOS interconnects. What differentiates this technology is its ability to locally and predictably engineer the electrical behavior of ALD TaN films without compromising the underlying material’s properties or the integrity of the device architecture. Unlike conventional methods that may require additional processing steps or thicker barrier layers, this approach leverages precise underlayer chemistry to achieve desired film properties within a continuous ALD process. This not only enhances the performance and scalability of superconducting Josephson junctions for quantum computing and superconducting digital logic circuits but also improves advanced CMOS interconnects by providing ultra-thin, effective diffusion barriers and etch-stop layers. The method’s versatility and fine-tuned control over material characteristics make it a significant advancement for next-generation electronic and quantum devices.
• Precise tuning of electrical properties of ALD tantalum nitride thin films through substrate surface modification.
• Enables selective, localized formation of conductive or highly resistive TaN films across a single wafer.
• Maintains ultra-thin modified underlayer critical for Cooper pair transparency in superconducting devices.
• Supports fabrication of high-resistivity insulating barriers for Josephson junctions in quantum computing and superconducting digital logic.
• Improves advanced CMOS interconnect performance by providing effective copper diffusion barriers and etch-stop layers.
• Allows spatial control of film characteristics without compromising superconducting or device fabrication requirements.
• Enhances reliability and performance of next-generation electronic and quantum devices through tailored material properties.
• Quantum computing Josephson junctions
• Single-flux quantum logic circuits
• Advanced CMOS interconnect barriers
• Ultra-thin copper diffusion barriers
• Selective etch-stop layer formation
PCT Application: PCT/US24/35793
US Patent Application: 19/497,801
EP Patent Application: TBD
CA Patent Application: TBD
TRL: 4
This technology is available for licensing.